Winner. Scientist of the Year 2024

Anantharaj Thalaimalai Vanaraj

Academic title, degree: B.E., M.Tech., Ph.D.
Fields of science: Semiconductors - CMOS VLSI
Research interest: CMOS VLSI Design Functional Verification and Post CMOS Technologies
Career Development: Senior
Organization: Samsung Austin Semiconductors
Position: Formal Verification Lead
City: San Jose, California
Country: USA

Dr. Anantharaj Thalaimalai Vanaraj earned his Bachelor of Engineering in Electronics and Communication Engineering from the Thanthai Periyar Government Institute of Technology, affiliated with Madras University, Vellore, Tamil Nadu. He went on to complete his Master of Technology in VLSI Systems from the National Institute of Technology (NIT), Tiruchirappalli, Tamil Nadu, and received his Ph.D. from NIT Tiruchirappalli in 2022.

With over 20 years of experience in ASIC, FPGA, and SOC development for consumer electronics, wireless, and storage applications, Dr. Vanaraj specializes in areas including NAND Flash Memory, Memory Architecture, CMOS VLSI Digital Design, VLSI Logic/Functional Verification, and Quantum-dot Cellular Automata (QCA) designs.

Currently, Dr. Vanaraj serves as the Formal Verification Lead at Samsung Austin Research Center – Advanced Computing Lab (SARC-ACL) in San Jose, California. He is part of the hardware design and development team responsible for Graphics Processing Unit (GPU) silicon-level design.

He brings extensive expertise in NAND Flash Memory design verification, utilizing IEEE 1800-based System Verilog and UVM. His contributions to the field are recognized by six US patents related to NAND Flash Memory and SSD products.

Dr. Anantharaj Thalaimalai Vanaraj has published over 15 research articles, which have been cited in more than 100 scholarly works. In addition to his research, he serves as a reviewer for several prestigious international journals and frequently delivers talks at international and national conferences, seminars, and workshops.

In April 2023, Dr. Anantharaj Thalaimalai Vanaraj reached a significant career milestone when he was elevated to the Senior grade by the Institute of Electrical and Electronics Engineers (IEEE) – Santa Clara Valley division, a recognition of his outstanding contributions to the field of electrical engineering. In July 2024, he was awarded a fellowship by the Institution of Electronics and Telecommunication Engineers (IETE).

Throughout 2024, Dr. Vanaraj published four groundbreaking research articles focusing on VLSI Design Functional Verification, Post-CMOS Quantum-dot Cellular Automata (QCA) designs, and Cybersecurity, showcasing his diverse expertise and contributions to advancing these critical areas of research.

In March 2024, Dr. Vanaraj presented a highly acclaimed paper, “SEQ Hierarchical Flow Setup of Clock Gating SOC Designs Towards Faster Convergence – A Case Study,” at the prestigious Synopsys User Group (SNUG) Silicon Valley Conference, held in Santa Clara, California.

In May 2024, he was invited to present another impactful paper, “Optimal Test Scenarios-Based Regression Suite for Functional Verification Closure of Advanced Digital Designs,” at the IEEE International Conference on Smart Systems for Applications in Electrical Sciences, organized by EIE Department of Siddaganga Institute of Technology, Tumkur, Karnataka, India.

Beyond his conference presentations, Dr. Vanaraj has contributed to the broader engineering community through thought leadership articles. In May and June 2024, he authored insightful LinkedIn articles such as “The 3 C’s of Formal Property-Based Verification” and “The Art of Comparing Apples to Oranges Using Formal Verification,” helping fellow professionals navigate complex verification processes.